1. Field of the Invention
The present invention relates in general to a semiconductor structural configuration for memory cells of high density mask ROM devices. In particular, the present invention relates to a semiconductor structural configuration for mask ROM devices having stacked CVD oxide architecture multi-state memory cells. More particularly, the present invention relates to stacked CVD oxide architecture multi-state memory cells each capable of storing more than one bit of data for increased data storage density.
2. Technical Background
Semiconductor read-only memory (ROM) devices, in particular, masked ROMs, are enjoying the advantages resulting from miniaturization advancements in semiconductor technology. Among the most significant accomplishments is the increase in memory storage capacity. More and more memory cells can be packed into the same semiconductor die area under commercial mass production conditions. During the evolution of device miniaturization, the architectural configuration of the mask ROM memory cell has undergone a series of changes, from the traditional two-state memory cell configurations to the x-cell, the flat cell, and, lately, the modified flat cell. These cell configuration improvements have propelled commercial mask ROM devices from the 128K, through 256K, and up to the 16M, even 32M-bit storage capacity levels. All these increasing capacity mask ROM devices are being manufactured into integrated circuits having reasonable and commercially feasible chip sizes.
However, under the restrictions imposed by general rules of layout for the construction of a mask ROM memory cell based on the conditions of the available technology, it is very difficult, if not impossible, to further reduce the size of the memory cell based on a single transistor. There is, so far, no other anticipated breakthrough, such as employing some other semiconductor structural configuration, which will replace the metal-oxide semiconductor (MOS) based memory cell.
A brief examination of the semiconductor structural configuration of the memory cell of a prior art mask ROM device helps to lay the foundation for the description of the present invention. FIG. 1 of the accompanying drawings schematically shows the top view of memory cells for a conventional mask ROM device. FIG. 2 schematically shows a cross section of the memory cells as fabricated on a semiconductor substrate which is taken along the II--II line of FIG. 1. Cross-referencing to the two drawing figures simultaneously helps demonstrate the limitations inherent in the prior art mask ROM memory cell when dimensional reduction is intended.
As is shown in FIGS. 1 and 2, prior art memory cells for a mask ROM device are fabricated on semiconductor substrate 10 of P-type conductivity. Heavily N-type implantation is then conducted to form source/drain regions 14 for the cells. Source/drain regions 14 extend in the vertical direction as is observed in the top view of FIG. 1, constituting the bit lines for the memory cells. Gate electrodes 16 are then formed over gate oxide layer 12 that covers the surface of silicon substrate 10. Gate electrodes 16 extend in the horizontal direction, perpendicular to the extending direction of source/drain regions 14, as can be seen in the top view. Gate electrodes 16 constitute the word lines for the memory cells. The formation of the word lines allows the area underneath a word line and between the two neighboring bit lines to be utilized as the channel region for the memory cell transistor. The conduction state of this transistor channel, that is, its status of either conducting or blocking, is sensed as the represented information bit of either "0" or "1" respectively for a memory cell in the mask ROM device.
The channel region conduction status can be programmed to contain the required program code bit assigned to that particular memory cell. In general, to facilitate the blocking of a channel region in a memory cell, P-type impurities may be implanted within the realm of this transistor channel region 18. The process of implanting these transistor channel regions for "programming" memory code-bit contents, generally referred to as code implanting, increases the threshold voltage for the implanted channel regions 18.
Such a mask ROM device employs a transistor as the core element for each of its memory cells, which can either of the "0" or "1" data bits. The operation of the transistor, however, relies on the certain prerequisite conditions that does not allow the physical dimension of the fabricated transistor memory cells to be reduced indefinitely.